(1) Field of the Invention
The invention relates to a method to form a DRAM memory device, and more particularly, to a method to improve isolation layer filling in a DRAM array in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
DRAM memory circuits are a basic building block for many electronic systems. A DRAM memory contains an array of densely-packed transistors with each transistor containing a charge storage capacitor. Packing density is a critical parameter in profitably producing DRAM circuits in a fiercely competitive marketplace. As manufacturers attempt to pack greater numbers of storage cells and connective lines into smaller die areas, many manufacturing challenges must be overcome.
Referring now to FIG. 1, a top view of a section of a partially completed DRAM memory circuit is shown. In this illustration, several features of a typical DRAM memory layout are depicted. First, active areas 10 and 22 are formed in the semiconductor substrate. Two gate conductor lines 14 overlie the semiconductor substrate and the active areas 10 and 22. Note particularly that the gate conductor lines 14 intersect the middle active areas 10 and form transistors. These gate conductor lines 14 are typically formed from polysilicon and may additionally contain sidewall spacers of, for example, silicon nitride or silicon dioxide to facilitate the formation of drain extensions.
In a typical DRAM cell design, the active areas are electrically isolated from each other. These active areas are ion implanted to form source and drain junctions for the cell transistors. To provide electrical connectivity to each bit line from the active area, bit line contacts 18 are made through any overlying isolation layer to each of the middle active areas 10 in the region between the adjacent gate conductor lines 14.
Note especially the area 26 between the two adjacent gate conductor lines 14 and the two adjacent bit line contacts 18. Two cross sectional representations of this area are illustrated in FIGS. 2 and 3.
Referring now particularly to FIG. 2, a first cross section is shown. The two adjacent gate conductor lines 14 are shown. Each gate conductor line 14 has sidewall spacers 30. After the DRAM transistor cells are formed, an insulating layer 34 is deposited overlying the semiconductor substrate 28 and the gate conductor lines 14 as shown. This insulating layer 34 may comprise any number of insulating materials, such as borophosphosilicate glass (BPSG).
By depositing a doped silicon dioxide material, it is easier to fill the very small space between the adjacent gate conductor lines 14. The aspect ratio of the gap is defined as the depth L2 of the gap divided by the width L1 of the gap. As DRAM designs and process technologies become smaller, the aspect ratio (L2/L1) becomes greater, especially in the bit line contact area. It becomes increasingly difficult, therefore, to completely fill the gap between the gate conductors 14. Keyholes or voids 38 can form in the critical area between the gate conductor lines as shown. These voids in the insulating layer 34 are not necessarily a problem because the air trapped in the voids can also act as an insulating material.
Referring now to FIG. 3, an alternative cross-section of the device is shown. In this cross-section, the adjacent middle bit lines 10 are highlighted. This cross section shows why the void 38 is a particular problem in this case. The void 38 forms a channel between the bit line contacts 18 for the adjacent active areas 10. When a conductive layer, such as polysilicon, is subsequently deposited to provide electrical connectivity, the two adjacent active areas 10 will be shorted together. This will result in a useless DRAM circuit.
Several prior art approaches disclose methods that use optical proximity correction (OPC) in the manufacture of integrated circuits. U.S. Pat. No. 6,060,368 to Hashimoto et al discloses an OPC-based method for correcting the dimensions of multiple material transistor gates. Specifically, buried channel MOS devices, some with n+ type polysilicon gates and some with p+ type polysilicon gates, may be simultaneously patterned. The OPC method independently corrects the polysilicon mask pattern for the n+ and the p+ regions by using correction tables. U.S. Pat. No. 5,663,017 to Schinella et al teaches a method and an apparatus to form large-scale integrated circuits fields comprising smaller, sub-fields. Sub-fields may be lithographically processed using independent processes and then stitched together. The method discloses use of OPC or of phase-shifting OPC. U.S. Pat. No. 5,553,273 to Liebmann shows an OPC method for gate arrays to reduce the critical dimension in selected areas.
A principal object of the present invention is to provide a very manufacturable method to form DRAM memory circuits in the manufacture of an integrated circuit device.
Another principal object of the present invention is to provide a very manufacturable DRAM transistor array device.
A further object of the present invention is to provide a method to prevent bit line contact to bit line contact shorts caused by voids in the insulating layer between adjacent gate conductor lines.
A yet further object is to selectively eliminate voids by selectively increasing the minimum distance between adjacent gate conductor lines in the critical regions where adjacent bit line contacts are also present.
Another further object of the present invention is to eliminate bit line contact to bit line contact shorts while maintaining device performance and not adding to processing complexity.
In accordance with the objects of this invention, a new method of forming gate conductor lines for a DRAM in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. Active areas are defined in the semiconductor substrate wherein planned DRAM transistors and bit lines will be formed. A gate conductor layer is deposited overlying the semiconductor substrate. The gate conductor layer is patterned to form gate conductor lines. The intersections of the gate conductor lines and the active areas form DRAM transistors. Adjacent gate conductor lines are spaced a first minimum distance in critical regions and are spaced a second minimum distance in non-critical regions. The critical regions are defined as the active areas between adjacent gate conductor lines where bit line contacts are planned. The non-critical regions are defined as areas located between the critical regions and the adjacent gate conductor lines. The second minimum distance is greater than the first minimum distance to thereby decrease the aspect ratio in the non-critical regions to less than the aspect ratio in the critical regions. An insulating layer is deposited overlying the gate conductor lines and the semiconductor substrate. The insulating layer completely fills the non-critical regions without creating voids to thereby eliminate bit line contact to bit line contact shorts without affecting transistor performance and to complete the formation of the gate conductor lines in the manufacture of the integrated circuit device.
Also in accordance with the objects of the present invention, a new DRAM transistor array device is achieved. The device comprises, first, active areas in a semiconductor substrate. Second, bit line contacts to the active areas pass through an insulating layer that overlies the semiconductor substrate. Finally, gate conductor lines overlie the insulating layer and the active areas. The intersection of the gate conductor lines and the active areas form the DRAM transistors. Adjacent gate conductor lines are spaced a first minimum distance in critical regions and are spaced a second minimum distance in non-critical regions. The critical regions are defined as the active areas between the adjacent gate conductor lines wherein the bit line contacts are formed. The non-critical regions are defined as areas located between the critical regions and the adjacent gate conductor lines. The second minimum distance is greater than the first minimum distance to thereby decrease the aspect ratio in the non-critical regions to less than the aspect ratio of the critical regions. Bit line contact to bit line contact shorts are thereby eliminated.